(1) Field of the Invention
This invention relates to an inter-bus communication interface device for transmitting/receiving data between a plurality of buses, and a data security device for carrying out secure communication, and more particularly to an inter-bus communication interface device for carrying out transfer of data via a buffer, and a data security device capable of carrying out cryptographic processing by using a hardware circuit.
(2) Description of the Related Art
Electronic equipment, such as a video camera and the like, sometimes includes an information processing unit for performing predetermined processing, in addition to a CPU (Central Processing Unit) for control of the whole equipment. For example, when electronic equipment is connected to a LAN (Local Area Network), a LAN interface containing the CPU can be mounted in the equipment to carry out highly sophisticated processing, such as encryption of communication data.
Data communication is carried out as required between an information processing unit containing the CPU (hereinafter referred to as the “internal CPU”) and an external host apparatus (hereinafter referred to as the “external host”) for control of the whole electronic equipment. The external host as well contains a CPU, and in an interface of various kinds of devices and apparatuses requiring data communication with such an external device or apparatus, a buffer called a FIFO (First-In First-Out) is generally used to secure transfer efficiency. The FIFO is a buffer of a type that outputs data in the order that the data are stored. Data transmitted/received between the external host and the internal CPU is once written in the FIFO, and then read out from the FIFO by the opposite party of communication.
FIG. 46 is a conceptual view showing a method employed by the internal CPU in receiving data from the external host. As shown in FIG. 46, a receive FIFO 920 for receiving data is disposed between the external host 910 and the internal CPU 930. In the illustrated example, it is assumed that the FIFO 920 includes a buffer area for storing data, and an interrupt-generating circuit for asserting an interrupt signal when the buffer area is full of data.
The external host 910 writes communication data into the FIFO 920 (step S101). Then, the FIFO 920 asserts an interrupt signal (step S102). The internal CPU 930 having detected the interrupt signal reads the communication data therein from the FIFO 920 (step S103).
FIG. 47 is a flowchart showing the procedure of operations executed in a process for receiving data from the external host by the internal CPU. In the following, the process shown in FIG. 47 will be described in the order of step numbers.
[Step S111] The external host 910 writes data into the FIFO 920. It should be noted that the external host 910 adds data end information to a trailing end of data to be transferred. After the data end information is added, when the FIFO 920 has an empty area, the external host 910 writes invalid data (e.g. data formed by only “0”) so as to fill the FIFO 920 becomes with data.
[Step S112] If the buffer area is not full of data by determination of the FIFO 920 as to whether or not the buffer area in the FIFO 920 is full of data, the step S111 is repeatedly carried out.
[Step S113] If the buffer area is full of data by determination of the FIFO 920 as to whether or not the buffer area in the FIFO 920 is full of data, the process proceeds to a step S114.
[Step S114] The FIFO 920 asserts an interrupt signal.
[Step S115] The internal CPU 930 reads out data in the FIFO 920, when it has detected the assertion of the interrupt signal.
[Step S116] When the FIFO 920 becomes empty of data, the internal CPU 930 terminates the reading of data, and the process proceeds to the step S111. After that, following data is written in the FIFO 920 by the external host 910.
[Step S117] Further, whenever the internal CPU 930 reads out data from the FIFO 920, it always checks whether or not the data read out is the data end information. When the data end information is detected, the internal CPU 930 terminates the data-receiving process.
FIG. 48 is a conceptual view showing a method employed by the internal CPU for transmitting data to the external host. As shown in FIG. 48, a transmit FIFO 940 for transmitting data is disposed between the external host 910 and the internal CPU 930. It should be noted that the FIFO 940 includes a buffer area for storing data, and a circuit for asserting a transmit data-related request signal when the buffer area is full of data.
The internal CPU 930 writes communication data in the FIFO 940 (step S121). Then, the FIFO 940 asserts the transmit data-related request signal (step S122). The external host 910 having detected the transmit data-related request signal reads the communication data therein from the FIFO 940 (step S123).
FIG. 49 is a flowchart showing the procedure of operations executed in a process for transmitting data to the external host by the internal CPU. In the following, the process shown in FIG. 49 will be described in the order of step numbers.
[Step S131] The internal CPU 930 writes data into the FIFO 940.
[Step S132] The FIFO 940 asserts the transmit data-related request signal.
[Step S133] The external host 910 reads data from the buffer area in the FIFO 940.
[Step S134] If the FIFO 940 is not empty, the external host 910 continues the reading of data in the step S133.
[Step S135] If the FIFO 940 becomes empty of data, the external host 910 terminates the reading of data.
As described above, the transmission/reception of data via the FIFO is carried out.
Although in the above example, the termination of writing of data into the FIFO 920 is notified by the assertion of the interrupt signal when data is transferred from the external host 910 to the internal CPU 930, this is not limitative, but the termination of writing of data into the FIFO 920 can be notified by another method. For example, if there is provided a request circuit for transmitting a reading request, a reading request can be transmitted via the circuit (as disclosed e.g. in Japanese Unexamined Patent Publication (Kokai) No. H11-18122, FIGS. 1 and 2).